1. Field of the Invention
The present invention relates to data storage systems and more particularly, to a method, apparatus and program storage device for providing a synchronous bus controller system.
2. Description of Related Art
In distributed computing systems a host computer typically controls and monitors rudimentary functions in other components of the distributed computing system, such as expansion enclosures or remote stations, using a minimal number of signals. Basic functions typically controlled by the host include indicators, switches, sensors, and generating simple waveforms. One conventional approach is to have independent direct connections between a host and remote stations. However, in high density modular systems like rack systems and blade systems, providing multiple direct connections between a host component and other components can create excessively complex cabling and wiring requirements.
To simplify wiring and cabling requirements hosts in modular systems often control components in the system using standard serial interfaces, such as a two wire I2C bus managed directly by the host. In such a system the host typically periodically individually addresses or polls devices on remote stations over a shared I2C bus. Various I2C devices are available for specific functions such as IO expanders which allow a host to generically manipulate and or sample signals on the remote stations.
A problem with conventional systems which use a bus like an I2C bus is the inability to tightly synchronize the assertion/de-assertion of signals via IO expanders on the various remote stations. To send a signal to a specific remote station, bus protocols like I2C specify the address of the target remote station and send signal packets including such addresses over the bus. A target remote station identifies a signal packet as being directed to it based on the address. The target remote station reads the content of signal packets addressed to it. To send a plurality of different signal packets to associated target remote stations, a host may generate and send such different signal packets individually to each of the corresponding target remote stations. Generating and sending such signal packets individually is one factor which can result in uncertainty in the timing of such signal packets reaching the different target remote stations. In addition, before a host completes generating and sending a group of such signal packets, the host process may be interrupted and the host may execute other instructions before resuming generating and sending the signal packets to the target remote stations. Such interrupts are another illustrative factor which can result in uncertainties in the timing of signal packets reaching different remote stations. These timing limitations of conventional systems can also result in such systems being incapable of generating sufficiently accurate waveforms at the remote stations, for example symmetric square waves with sufficiently accurately defined pulse width and duty cycle.
It can be seen that there is a need to provide an improved bus controller system with better control of signal timing.